Selecting a good generic CacheEdge

ATLAS uses the CacheEdge macro set in BLDdir/include/atlas_cacheedge.h and atlas_tcacheedge.h to control the L2-cache blocking for the serial and threaded libraries, respectively. You'll want to be sure this value is either set to the minimum of the L2SIZE of any target architecture, or ridiculously large, so that no effective L2 blocking is done. So, if you are using non-celeron x86, it almost always safe to set this value (in both files) to 256K (262144), since almost all archs have at least this much cache. If you know your target machines have more cache than this, then increase this number appropriately. If you may have celerons or other archs with crippled last-level caches, then I recommend you set CacheEdge to 4194304 (4MB). At this level, CacheEdge doesn't effectively block for caches, but it will tend to keep your workspace requirements down.

R. Clint Whaley 2016-07-28